1. Field of the Invention
The present invention relates to a semiconductor device provided with a plurality of semiconductor elements, and more particularly to a semiconductor device provided with a plurality of semiconductor elements having different threshold voltages.
2. Description of the Background Art
In a semiconductor device provided with a plurality of semiconductor elements, there are cases where semiconductor elements having their threshold voltages (Vth) set different from one another are required.
A first case where such semiconductor elements having different threshold voltages (Vth) are required is as follows. In recent years, semiconductor devices having lower threshold voltages have been desired, because of increasing demands for reduction of power consumption, widening of applications of handheld equipment, securing of device reliability, and thus, the devices need to operate at low voltages (of not greater than 1 V, for example). Reduction of the threshold voltage, however, leads to an increase of sub-threshold leakage in a semiconductor element. To solve the problem, Nippon Telegraph and Telephone Corporation has developed a MT (Multi)-CMOS (Complementary Metal Oxide Semiconductor) circuit.
In a second case, semiconductor elements having different threshold voltages (Vth) are required to restrict occurrence of channel leakage in a narrow channel width transistor. In a semiconductor device having a logic circuit with an SRAM (Static Random Access Memory) built therein, it is common to make the channel width (W1) of a transistor constituting the SRAM portion narrower than the channel width (W2) of a transistor constituting a peripheral logic circuit system, to limit the area dedicated to the SRAM portion.
When a transistor having such a narrow channel width is employed, however, channel leakage increases more in the SRAM portion than in the peripheral logic circuit, specifically in a p channel transistor (Vth_typ), and especially in a low-threshold voltage (Vth) transistor (Vth_L), as shown in FIG. 19. This is presumably because the low threshold voltage of the narrow channel width transistor is decreased due to stress from an isolation insulating film region or the like.
FIG. 19 schematically shows a relation of Vg (gate voltage)xe2x80x94Id (drain current) of a p channel transistor. Channel leakage corresponds to a sub-threshold leakage value |log Ids| when Vg=0, as shown as Ioff in FIG. 19. As shown in FIG. 20, the channel leakage tends to increase in the narrow channel width transistor with a lower threshold voltage condition.
As described above, in a transistor used in a semiconductor device, threshold voltage setting is changed by changing dopant impurity concentration of a channel region. To change the impurity concentration of the channel region, it is necessary to cover with a resist mask a region other than a transistor forming region of a transistor having a threshold voltage to be changed, and to introduce a dopant impurity into the transistor forming region to change the threshold voltage. With this method, however, the number of manufacturing steps, WP TAT (Wafer Process Turn Around Time), and manufacturing cost of the semiconductor device will all increase.
An object of the present invention is to provide a semiconductor device having semiconductor elements of different threshold voltages, without increasing the number of manufacturing steps and others.
According to an aspect of the semiconductor device based on the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having the same conductivity type as the first active region and provided in the first active region to sandwich the first gate electrode; second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region; third impurity diffusion regions having a different conductivity type from the second impurity diffusion regions and each provided in respective one of the second impurity diffusion regions in a region shallower than a diffusion depth of the second impurity diffusion region; and fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion regions and each provided in respective one of the third impurity diffusion regions in a region shallower than a diffusion depth of the third impurity diffusion region.
The second semiconductor element includes: a second active region having the same conductivity type as the first active region and provided in the semiconductor substrate; a second gate electrode provided on the second active region with a second gate insulating film interposed therebetween; a pair of fifth impurity diffusion regions corresponding to the first impurity diffusion regions and having the same conductivity type as the first impurity diffusion regions; sixth impurity diffusion regions corresponding to the third impurity diffusion regions and having the same conductivity type as the third impurity diffusion regions; and seventh impurity diffusion regions corresponding to the fourth impurity diffusion regions and having the same conductivity type as the fourth impurity diffusion regions.
Further, the first semiconductor element constitutes a transistor for use in a memory cell region, and the second semiconductor element constitutes a transistor for use in a peripheral circuit region. A first total impurity concentration of the first impurity diffusion region and the second impurity diffusion region in the first semiconductor element is set higher than a second total impurity concentration of the fifth impurity diffusion region in the second semiconductor element.
With this configuration, the first total impurity concentration constituting, e.g., an SPI (Shallow Pocket Implant) region of the first semiconductor element is set higher than the second total impurity concentration constituting, e.g., the SPI region of the second semiconductor element. Thus, it is possible to restrict channel leakage in the first semiconductor element used in the memory cell region to the same degree as in the second semiconductor element.
According to another aspect of the semiconductor device based on the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having the same conductivity type as the first active region and provided in the first active region to sandwich the first gate electrode; second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region; third impurity diffusion regions having a different conductivity type from the second impurity diffusion regions and each provided in respective one of the second impurity diffusion regions in a region shallower than a diffusion depth of the second impurity diffusion region; and fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion regions and each provided in respective one of the third impurity diffusion regions in a region shallower than a diffusion depth of the third impurity diffusion region.
The second semiconductor element includes: a second active region having the same conductivity type as the first active region and provided in the semiconductor substrate; a second gate electrode provided on the second active region with a second gate insulating film interposed therebetween; a pair of fifth impurity diffusion regions corresponding to the first impurity diffusion regions and having the same conductivity type as the first impurity diffusion regions; sixth impurity diffusion regions corresponding to the third impurity diffusion regions and having the same conductivity type as the third impurity diffusion regions; and seventh impurity diffusion regions corresponding to the fourth impurity diffusion regions and having the same conductivity type as the fourth impurity diffusion regions.
Further, the first semiconductor element has a first threshold voltage, and the second semiconductor element has a second threshold voltage that is lower than the first threshold voltage. A first total impurity concentration of the first impurity diffusion region and the second impurity diffusion region in the first semiconductor element is set higher than a second total impurity concentration of the fifth impurity diffusion region in the second semiconductor element. An impurity concentration distribution in the first active region beneath the first gate electrode of the first semiconductor element is approximately the same as an impurity concentration distribution in the second active region beneath the second gate electrode of the second semiconductor element.
With this configuration, it is possible to set a difference in threshold voltage between the first and second semiconductor elements, only by the difference in impurity concentration between the SPI region in the first semiconductor element formed of the first and second impurity diffusion regions and the SPI region in the second semiconductor element formed of the fifth impurity diffusion region.
According to a further aspect of the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having the same conductivity type as the first active region and provided in the first active region to sandwich the first gate electrode; second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region; third impurity diffusion regions having a different conductivity type from the second impurity diffusion regions and each provided in respective one of the second impurity diffusion regions in a region shallower than a diffusion depth of the second impurity diffusion region; and fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion region and each provided in respective one of the third impurity diffusion regions in a region shallower than a diffusion depth of the third impurity diffusion region.
The second semiconductor element includes: a second active region having the same conductivity type as the first active region and provided in the semiconductor substrate; a second gate electrode provided on the second active region with a second gate insulating film interposed therebetween; a pair of fifth impurity diffusion regions corresponding to the first impurity diffusion regions and having the same conductivity type as the first impurity diffusion regions; sixth impurity diffusion regions corresponding to the third impurity diffusion regions and having the same conductivity type as the third impurity diffusion regions; and seventh impurity diffusion regions corresponding to the fourth impurity diffusion regions and having the same conductivity type as the fourth impurity diffusion regions.
Further, a gate width of the first semiconductor element is set narrower than a gate width of the second semiconductor element, and a film thickness of the first gate oxide film of the first semiconductor element is set greater than a film thickness of the second gate oxide film of the second semiconductor element.
With this configuration, not only the impurity concentration of the SPI region in the first semiconductor element formed of the first and second impurity diffusion regions is differentiated from that of the SPI region in the second semiconductor element formed of the fifth impurity diffusion region, but also the film thicknesses of the gate oxide films in the first and second semiconductor elements are differentiated from each other. Accordingly, it is possible to further increase the difference in threshold voltage between the first and second semiconductor elements.
According to yet another aspect of the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having a different conductivity type from the first active region and provided in the first active region to sandwich the first gate electrode; and second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region.
The second semiconductor element includes: a second active region provided in the semiconductor substrate; a second gate electrode provided on the second active region with a second gate insulating film interposed therebetween; a pair of third impurity diffusion regions having the same conductivity type as the second active region and provided in the second active region to sandwich the second gate electrode; fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion regions and each provided in respective one of the third impurity diffusion regions in a region shallower than a diffusion depth of the third impurity diffusion region; fifth impurity diffusion regions having a different conductivity type from the fourth impurity diffusion regions and each provided in respective one of the fourth impurity diffusion regions in a region shallower than a diffusion depth of the fourth impurity diffusion region; and sixth impurity diffusion regions having the same conductivity type as the fifth impurity diffusion regions and each provided in respective one of the fifth impurity diffusion regions in a region shallower than a diffusion depth of the fifth impurity diffusion region.
Further, in the semiconductor device, the diffusion depth of the first impurity diffusion region from the surface of the first active region is equal to the diffusion depth of the third or fourth impurity diffusion region from the surface of the second active region.
As such, the second semiconductor element is provided with the third, fourth, fifth and sixth impurity diffusion regions. The third impurity diffusion region located outermost constitutes the SPI region, and the fourth impurity diffusion region locally increases the impurity concentration of this SPI region, whereby the threshold voltage of the second semiconductor element is increased. As a result, the semiconductor device of the present invention is applicable to a semiconductor device having both a first semiconductor element unprovided with an SPI region and a second semiconductor element provided with the SPI region, e.g., as a portion of the source/drain region.
In a preferred embodiment of the semiconductor device, the first semiconductor element is an n channel type semiconductor element having the first active region of p conductivity type, and the second semiconductor element is a p channel type semiconductor element having the second active region of n conductivity type.
In another preferred embodiment, the film thickness of the first gate insulating film of the first semiconductor element is different from that of the second gate insulating film of the second semiconductor element. For example, when the semiconductor device of the present invention is adapted to a semiconductor device having an external type transistor and an internal type transistor having different operating voltages, the first gate insulating film of the first semiconductor element is made thicker than the second gate insulating film of the second semiconductor element.
In yet another preferred embodiment, the semiconductor device is further provided with a third semiconductor element of the same channel type as the second semiconductor element. The third semiconductor element includes: a third active region of the same conductivity type as the second active region and provided in the semiconductor substrate; a third gate electrode provided on the third active region with a third gate insulating film interposed therebetween; a pair of seventh impurity diffusion regions corresponding to the third impurity diffusion regions and having the same conductivity type as the third impurity diffusion regions; eighth impurity diffusion regions corresponding to the fifth impurity diffusion regions and having the same conductivity type as the fifth impurity diffusion regions; and ninth impurity diffusion regions corresponding to the sixth impurity diffusion regions and having the same conductivity type as the sixth impurity diffusion regions.
Although the third semiconductor element has the seventh impurity diffusion region constituting the SPI region similar to the third impurity diffusion region of the second semiconductor element, it does not have an impurity diffusion region corresponding to the fourth impurity diffusion region of the second semiconductor element. As a result, in the semiconductor device, it is possible to change the threshold voltages of the second and third semiconductor elements having the SPI regions.
In an aspect of a manufacturing method of a semiconductor device according to the present invention, the manufacturing method of a semiconductor device provided with a first semiconductor element and a second semiconductor element of a different channel type from the first semiconductor element includes the steps of: forming an element isolating insulating film in a prescribed region of a semiconductor substrate to define a first active region and a second active region of a different conductivity type from the first active region; forming a first gate electrode on the first active region with a first gate insulating film interposed therebetween and forming a second gate electrode on the second active region with a second gate insulating film interposed therebetween; introducing impurity of a first conductivity type into the first active region, with the first gate electrode used as a mask, to form a pair of first impurity diffusion regions having a different conductivity type from the first active region, and also introducing impurity of the first conductivity type into the second active region, with the second gate electrode used as a mask, to form a pair of fourth impurity diffusion regions having the same conductivity type as the second active region; introducing impurity of the first conductivity type into the second active region alone, with the second gate electrode used as a mask, to form a third impurity diffusion region surrounding the fourth impurity diffusion region and having an impurity diffusion depth deeper than the fourth impurity diffusion region; introducing impurity of the second conductivity type into the second active region alone, with the second gate electrode used as a mask, to form a fifth impurity diffusion region having an impurity concentration greater than that of the fourth impurity diffusion region; forming sidewall insulating films on respective sidewalls of the first and second gate electrodes; introducing impurity of the second conductivity type into the second active region alone, with the second gate electrode and the sidewall insulating film used as masks, to form a sixth impurity diffusion region in the fifth impurity diffusion region at an impurity diffusion depth that is shallower than that of the fifth impurity diffusion region; introducing impurity of the first conductivity type into the first active region alone, with the first gate electrode and the sidewall insulating film used as masks, to form a second impurity diffusion region in the first impurity diffusion region at an impurity diffusion depth that is shallower than that of the first impurity diffusion region.
The manufacturing method described above brings about a structure in which the second semiconductor element is provided with the third, fourth, fifth and sixth impurity diffusion regions, the third and fourth impurity diffusion regions constitute an SPI region, and the impurity concentration in this SPI region is locally increased as the impurities in the third and fourth impurity diffusion regions are added together. The fourth impurity diffusion region is formed at the same time as the step of forming the first impurity diffusion region in the first semiconductor element. This eliminates the need for an additional step of forming the fourth impurity diffusion region. As a result, a semiconductor device provided with a plurality of semiconductor elements having different threshold voltages can be manufactured without increasing a number of manufacturing steps, WP TAT, or manufacturing cost of the semiconductor device.
In a preferred embodiment of the manufacturing method of the semiconductor device described above, the first semiconductor element is an n channel type semiconductor device having the first active region of a p conductivity type, and the second semiconductor element is a p channel type semiconductor device having the second active region of an n conductivity type. The impurity of the first conductivity type is n type impurity, and the impurity of the second conductivity type is p type impurity.
In another preferred embodiment, the first gate insulating film of the first semiconductor element is formed to have a film thickness that is different from that of the second gate insulating film of the second semiconductor element.
In another aspect of the manufacturing method of a semiconductor device according to the present invention, the manufacturing method of a semiconductor device provided with a first semiconductor element, a second semiconductor element having a different channel type from the first semiconductor element and a third semiconductor element having the same channel type as the second semiconductor element includes the steps of: forming an element isolating insulating film in a prescribed region of a semiconductor substrate to define a first active region, a second active region having a different conductivity type from the first active region, and a third active region having the same conductivity type as the second active region; forming a first gate electrode on the first active region with a first gate insulating film interposed therebetween, forming a second gate electrode on the second active region with a second gate insulating film interposed therebetween and forming a third gate electrode on the third active region with a third gate insulating film interposed therebetween; introducing impurity of a first conductivity type into the second and third active regions, with the second and third gate electrodes used as masks, to form a pair of third impurity diffusion regions and a pair of seventh impurity diffusion regions having the same conductivity type as the second and third active regions; introducing impurity of a second conductivity type into the second and third active regions, with the second and third gate electrodes used as masks, to form fifth and eighth impurity diffusion regions in the third and seventh impurity diffusion regions, respectively, at impurity diffusion depths shallower than those of the third and seventh impurity diffusion regions; forming sidewall insulating films on sidewalls of the first gate insulating film and the first gate electrode, the second insulating film and the second gate electrode and the third gate insulating film and the third gate electrode; introducing impurity of the first conductivity type into the first and second active regions, with the first gate electrode and the corresponding sidewall insulating film, and the second gate electrode and the corresponding sidewall insulating film used as masks, to form second and fourth impurity diffusion regions in the first and third impurity diffusion regions, respectively, at impurity diffusion depths shallower than those of the first and third impurity diffusion regions; and introducing impurity of the second conductivity type into the second and third active regions, with the second gate electrode and the corresponding sidewall insulating film, and the third gate electrode and the corresponding sidewall insulating film used as masks, to form sixth and ninth impurity diffusion regions in the fifth and eighth impurity diffusion regions, respectively, at impurity diffusion depths shallower than those of the fifth and eighth impurity diffusion regions.
Although the third semiconductor element obtained with these steps has the seventh impurity diffusion region which constitutes the SPI region as does the third impurity diffusion region of the second semiconductor element, it does not have an impurity diffusion region corresponding to the fourth impurity diffusion region of the second semiconductor element. As a result, it is possible to provide a semiconductor device with a second semiconductor element and a third semiconductor element having different threshold voltages because of different concentrations of their SPI regions.